I'm Ashmita Chakraborty

This project is a cutting-edge, non-invasive wearable medical platform that integrates clinical-grade monitoring directly into everyday garments through specialized 'textrodes'. The system leverages Thoracic Electrical Bioimpedance (TEB) and high-fidelity ECG to track heart muscle electrophysiologic patterns, respiratory rate, and oxygen saturation. Built on a Zephyr RTOS-based architecture utilizing the AD5940 chipset, the firmware features a DFT-based impedance measurement pipeline, real-time BLE telemetry, and low-power sequencers designed to support non-blocking periodic sampling and logarithmic frequency sweeps for deep physiological analysis

Oversynchronisation of GPUs : This research work is about investigating 'over-synchronization' in CUDA programs—a performance bottleneck where developers use wider synchronization scopes than necessary for correctness. The study outlines the interplay between the PTX memory consistency model and GPU hardware behaviors (like L1 or L1 cache bypassing). It investigates how redundant device-scoped fences and atomic RMW instructions impact throughput, leading to the development of a dynamic analysis tool that improves GPU library performance by up to 55%. Model-based System Engineering : This research work is about investigating robust control strategies for ground robots to achieve precise trajectory tracking while maintaining safety. The study outlines the integration of Sliding Mode Control (SMC) to handle system disturbances and Control Barrier Functions (CBF) to ensure real-time obstacle avoidance. It investigates the mapping of optimized control inputs from double-integrator models to unicycle kinematics, validated through experimental testing on differential drive robots using in-house camera-based localization

This project-research work is about investigating the feasibility of a distributed edge computing architecture designed to overcome intermittent connectivity in aviation environments, and developing a decentralized network where cabin crew devices function as mobile edge nodes to preprocess and aggregate data from onboard services during flight. The project makes use of Delay Tolerant Networking (DTN) bundle protocols and IEEE 802.11 standards to facilitate efficient data offloading to terrestrial back-end servers upon landing. By conducting a comparative analysis with frameworks like Kubernetes, it develops and validates the system design requirements for low-latency, cost-effective data synchronization and prototype validation under simulated in-flight conditions

The project outlines the design and scoping of an AR/VR-based use case for large-scale vehicles, such as airplanes and trains, utilizing discreet haptic cues in wearables and portable devices for intuitive wayfinding. It further investigates the conceptualization of 'Oreo’s Cyberquest Safari,' a product that employs structural semiotic analysis and object identification to facilitate remote navigation and immersive information presentation. Through collaborative UI/UX research and Functional-Behaviour-Structure (FBS) modeling, the project is built by exploring how multi-modal feedback dynamics can be utilized to create seamless, interactive wayfinding experiences across diverse market segments

The project Systevo Touch IP is a centralized hospital communication hub built on an ARM A53 quad-core architecture. It focuses on transitioning traditional nurse-call signaling into a high-performance VoIP/SIP platform, featuring the development of full-duplex audio, half-duplex audio and advanced echo cancellation

The project outlines the implementation of critical system-level features—Subsystem Reset (SSR) and Hands-Free Profile (HFP).The project investigates methods for fault-tolerant computing within the audio processor. It outlines the development of an SSR framework designed to detect DSP-side crashes and orchestrate an independent recovery of the audio subsystem. And the work of HFP feature development investigates the end-to-end voice path within the Signal Processing Framework (SPF). It outlines the development of Hands-Free Profile (HFP) support in HAL layer, utilizing the Common Audio Processing Interface (CAPI) to manage complex voice topologies. The project investigates the synchronization of host-side Bluetooth protocols with embedded DSP firmware to enable low-latency, high-fidelity concurrent PCM transcoding for wearable platforms

The Qualcomm Aware Platform project is a cloud-native industrial IoT ecosystem designed for real-time asset intelligence and supply chain visibility. The project leveraged the platform’s API-first architecture to integrate multi-modal sensor data—including temperature, tilt, and motion—with high-accuracy terrestrial (Wi-Fi/Cellular) and GNSS positioning services.It is developed within a secure, end-to-end connectivity framework, utilizing Aware Signalling Protocol (ASP) and CoAP for power-optimized device-to-cloud telemetry

This project involved developing features for the server system - the Secure Debug Unlock and Microcode Patching infrastructure, on AMD Daytona and Ethanol or, EthanolX boards. The work centered on designing a secure HLD/LLD interface, and developing the code for the same, that allows authenticated access to sensitive security processor registers via the Hardware Debug Tool (HDT), preventing unauthorized hardware-level intrusion. It further integrated microcode complex patching and the APEX architecture, which utilizes BMC controllers for remote diagnostics, power state manipulation, and automated firmware testing to ensure platform integrity in high-scale data center environments

This project involved the end-to-end porting and optimization of the Android Automotive OS (AAOS) onto the Gordon Peak hardware platform. It focused on establishing the Android BSP (Board Support Package) and managing version upgrades from Android 9 through Android 11 (Android R). Key technical work included customizing the OS abstraction layer, integrating Kernel CVE patches, and optimizing the Camera HAL and graphics rendering modules for in-vehicle performance. The project also addressed complex system-level debugging, such as resolving bootloader image regressions and IFWI (Integrated Firmware Image) deployment issues to ensure a stable, production-ready infotainment environment

This project involved the custom BIOS development and system bring-up for a COM Express Type 7 module based on the Intel Xeon D-1559 processor. The work focused on porting the Coreboot framework and EDK2 source to create a secure, high-speed 8MB boot image, utilizing the Intel Firmware Support Package (FSP) for the Grangeville platform, developing the firmware code for the PCI/PCIe devices. Key achievements included optimizing the boot flow to achieve a sub-2-second startup time, developing EDK2 drivers for hardware monitoring (thermal, voltage, and SMBus telemetry), and stitching UEFI payloads with ME binaries to ensure a production-ready server platform